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rev. 0 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 ad8328 * 5 v upstream cable line driver features supports docsis and eurodocsis standards for reverse path transmission systems gain programmable in 1 db steps over a 59 db range low distortion at 60 dbmv output: C 57.5 dbc sfdr at 21 mhz C 54 dbc sfdr at 65 mhz output noise level @ minimum gain 1.2 nv/ hz maintains 300 output impedance tx-enable and transmit-disable condition upper bandwidth: 107 mhz (full gain range) 5 v supply operation supports spi interfaces applications docsis and eurodocsis cable modems catv set-top boxes catv telephony modems coaxial and twisted pair line driver general description t he ad8328 is a low cost amplifier designed for coaxial line driving. the features and specifications make the ad8328 ideally suited for mcns-docsis and euro-docsis applica- tions. the gain of the ad8328 is digitally controlled. an 8-bit serial word determines the desired output gain over a 59 db range, resulting in gain changes of 1 db/lsb. the ad8328 accepts a differential or single-ended input signal. the output is specified for driving a 75 ? load through a 2:1 transformer. distortion performance of C 53 dbc is achieved with an output level up to 60 dbmv at 65 mhz bandwidth over a wide tempera- ture range. this device has a sleep mode function that reduces the quiescent current to 2.6 ma and a full power-down function that reduces power-down current to 20 a. th e ad8328 is packaged in a low cost 20-lead lfcsp package and a 20-lead qsop package. the ad8328 operates from a single 5v supply and has an operational temperature range of C 40 c to +85 c. functional block diagram diff or single input amp attenuation core z out diff = 300 8 8 8 z in (single) = 800 z in (diff) = 1.6k ad8328 daten sdata clk txen sleep v out+ v out v in+ v in vernier decode data latch shift register power-down logic power amp byp gnd ramp 5 15 25 35 45 55 65 distortion ?dbc frequency ?mhz v out = 60dbmv @max gain, third harmonic v out = 60 dbmv @max gain, second harmonic ?0 ?8 ?6 ?4 ?2 ?0 ?8 ?6 ?4 ?2 ?0 figure 1. worst harmonic distortion vs. frequency * patent pending
rev. 0 e2e ad8328 especifications parameter conditions min typ max unit input characteristics specified ac voltage output = 60 dbmv, max gain 29 dbmv input resistance single-ended input 800 differential input 1600 input capacitance 2pf gain control interface voltage gain range 58 59.0 60 db max gain gain code = 60 dec 30.5 31.5 32.5 db min gain gain code = 1 dec ? 28.5 ? 27.5 ? 26.5 db output step size 0.6 1.0 1.4 db/lsb output step size temperature t a = ? 40 c to +85 c 0.0005 db/ c coefficient output characteristics bandwidth ( ? 3 db) all gain codes (1 ? 60 decimal codes) 107 mhz bandwidth roll-off f = 65 mhz 1.2 db 1 db compression point 2 max gain, f = 10 mhz, output referred 17.9 18.4 dbm min gain, f = 10 mhz, input referred 2.2 3.3 dbm output noise 2 max gain f = 10 mhz 135 151 nv/ hz hz hz td hz hz n hz d tetd eallpeane shd hz t hz t thd hz t hz t ap td hz pentl test n tdst n st e e s d ds n pesppl a a tdten a sleep pd a peatntepeate ane ntes tptthz z t a s z t a n pssps t a s l n n d tadz
rev. 0 ad8328 e3e logic inputs (ttl/cmos compatible logic) parameter min typ max unit logic 1 voltage 2.1 5.0 v logic 0 voltage 0 0.8 v logic 1 current (v inh = 5 v) clk, sdata, daten a l nl lsdata daten a l nh ten a l nl ten a l nh sleep a l nl sleep a s tneeents p t p h p stsdata ds st daten es htsdata dh ht daten eh tsdata daten s es alddatad sls antanse ds eh lles antanse s anal tpt snalapltde ten l sdata daten n h alddatad st alddatat s s s ds dh sdata l sdatat t l hz daten lsdataten s leep t
rev. 0 e4e ad8328 absolute maximum ratings * supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v input voltage vin+, vin ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 v p-p daten sdatal sleep ten pd splsp t st lts sa t e atn esde a adesd tesd pnnatns dende t pd a p ada lsp adaeel lsp adaeal e adap llsp p adapeel llsp p adapeal e tse tse l sp tpe ns ad ten sdata l n sleep p n t nnnnet nd nd nd n nd ap t nd daten nd l lsp tpe ns ad nd nd nd n n nd nd ten nd sleep daten sdata l ap t t p n pnntndesptns pn pn l l lsp sp d nd e pesa n nd s n d s daten deltal a sdata sdt s l t a l t sleep lpssad a a l h t sl p t t ns t ps ap eap ten ll
rev. 0 t ypical performance characteristicsead8328 e5e frequency e mhz distortion e dbc 5 15 25 35 45 55 65 65 55 75 v out = 59dbmv @max gain v out = 60dbmv @max gain v out = 61dbmv @max gain 60 70 tpc 1. second-order harmonic distortion vs. frequency for various output powers frequency e mhz distortion e dbc e50 e55 e75 515 65 25 35 45 55 e60 e65 e70 t a = +25 c t a = +85 c t a = e40 c v out = 60dbmv @ max gain tpc 2. second-order harmonic distortion vs. frequency vs. temperature 10 0 e10 e20 e30 e40 e50 e60 e70 e80 e90 span 750khz 75khz/div 60dbmv e58.2db ch pwr acp cu1 cu1 c0 c0 c11 c11 p out e dbm tpc 3. adjacent channel power v out = 60dbmv @max gain frequency e mhz distortion e dbc 5 15 25 35 45 55 65 60 50 70 v out = 59dbmv @max gain v out = 61dbmv @max gain 55 65 tpc 4. third-order harmonic distortion vs. frequency for various output powers frequency e mhz e50 e55 e65 565 15 distortion e dbc 25 35 45 55 e60 t a = +85 c t a = +25 c t a = e40 c v out = 60dbmv @ max gain tpc 5. third-order harmonic distortion vs. frequency vs. temperature frequency e mhz e40 41.6 v out e dbmv e30 e20 e10 0 10 20 30 40 50 60 41.7 41.8 41.9 42 42.1 42.2 42.3 v out = 57dbmv/tone @ max gain 42.4 42.5 tpc 6. two-tone intermodulation distortion
rev. 0 e6e ad8328 40.0 30.0 20.0 10.0 0 e10.0 e20.0 e30.0 e40.0 0.1 1 10 100 1000 gain e db frequency e mhz dec60 dec54 dec48 dec24 dec36 dec42 dec30 dec12 dec18 dec 1 to dec 6 tpc 7. ac response gain control e decimal code output step size e db 0612 18 24 30 36 42 48 54 60 1.4 1.2 1.0 0.8 0.6 f = 10mhz tpc 8. output step size vs. gain control output referred voltage noise e nv/ hz 0612 18 24 30 36 42 48 54 60 gain control e decimal code 140 120 100 80 60 40 20 0 f = 10mhz txen = 1 tpc 9. output referred voltage noise vs. gain control 1 10 100 1000 isolation e db frequency e mhz 90 100 80 70 60 50 40 30 20 10 0 txen = 0 v in = 29dbmv max gain min gain tpc 10. isolation in transmit disable mode vs. frequency f = 5mhz f = 42mhz f = 65mhz gain control e decimal code gain error e db 0612 18 24 30 36 42 48 54 60 1.6 1.2 0.8 0.4 0 0.4 0.8 1.2 1.6 f = 10mhz tpc 11. gain error vs. gain control quiescent supply current e ma 0102030405060 130 gain control e decimal code 120 100 80 60 50 30 20 110 90 70 40 tpc 12. supply current vs. gain control
rev. 0 ad8328 e7e v in+ v ine v cc gnd ad8328 byp r l 5v 1 2 1 2 v in v in v out+ v oute figure 4. characterization circuit applications general applications the ad8328 is primarily intended for use as the power amplifier (pa) in docsis (data over cable service interface specification) certified cable modems and catv set-top boxes. the upstream signal is either a qpsk or qam signal generated by a dsp, a dedicated qpsk/qam modulator, or a dac. in all cases, the signal must be low-pass filtered before being applied to the pa in order to filter out-of-band noise and higher order harmonics from the amplified signal. due to the varying distances between the cable modem and the head-end, the upstream pa must be capable of varying the output power by applying gain or attenuation. the ability to vary the output power of the ad8328 ensures that the signal from the cable modem will have the proper level once it arrives at the head-end. the upstream signal path commonly includes a diplexer and cable splitters. the ad8328 has been designed to overcome losses asso- ciated with these passive components in the upstream cable path. circuit description the ad8328 is composed of three analog functions in the power-up or forward mode. the input amplifier (preamp) can be used single- ended or differentially. if the input is used in the differential configuration, it is imperative that the input signals be 180 degrees out of phase and of equal amplitude. a vernier is used in the input stage for controlling the fine 1 db gain steps. this stage then drives a dac, which provides the bulk of the ad8328 ? s attenuation. the signals in the preamp and dac gain blocks are differential to improve the psrr and linearity. a differential current is fed from the dac into the output stage. the output stage maintains 300 differential output impedance, which maintains proper match to 75 when used with a 2:1 balun transformer. spi programming and gain adjustment the ad8328 is controlled through a serial peripheral interface (spi) of three digital data lines: clk, daten sdata sdatatsdata daten ll sdata lst daten t tad t ad lst tadz tpt tad tpt t t n n t ad tad tad t tadt a daten sdata l sleep n nd n n p ad sp ten sleep nd nd nd nd ten ap t t nd tdplee n tpt daten sdata l n n n ta
rev. 0 e8e ad8328 the output impedance of the ad8328 is 300 , regardless of whether the amplifier is in transmit enable or transmit disable mode. this, when combined with a 2:1 voltage ratio (4:1 im ped- ance ratio) transformer, eliminates the need for external back termination resistors. if the output signal is being evaluated using standard 50 test equipment, a minimum loss 75 ? 50 pad must be used to provide the test circuit with the proper impedance match. the ad8328 evaluation board provides a convenient means to implement a matching attenuator. soldering a 43.3 resistor in the r15 placeholder and an 86.6 resistor in the r16 placeholder will allow testing on a 50 system. when using a matching attenuator, it should be noted that there will be a 5.7 db of power loss (7.5 db voltage) through the network. power supply the 5 v supply should be delivered to each of the v cc pins via a low impedance power bus to ensure that each pin is at the same potential. the power bus should be decoupled to ground using a 10 f tantalum capacitor located close to the ad8328. in addition to the 10 f capacitor, each v cc pin should be indi- vidually decoupled to ground with ceramic chip capacitors located close to the pins. the bypass pin, labeled byp, should also be decoupled. the pcb should have a low impedance ground plane covering all unused portions of the board, except in areas of the board where input and output traces are in close proximity to the ad8328 and the output transformer. all ad 8328 ground pins must be connected to the ground plane to ensure proper grounding of all internal nodes. signal integrity layout considerations careful attention to printed circuit board layout details will prevent problems due to board parasitics. proper rf design techniques are mandatory. the differential input and output traces should be kept as short as possible. keeping the traces short will minimize parasitic capacitance and inductance. this is most critical between the outputs of the ad8328 and the 2:1 output transformer. it is also critical that all differential signal paths be symmetrical in length and width. in addition, the input and output traces should be adequately spaced to minimize coupling (crosstalk) through the board. following these guide- lines will optimize the overall performance of the ad8328 in all applications. initial power-up when the supply voltage is first applied to the ad8328, the gain of the amplifier is initially set to gain code 1. as power is first applied to the amplifier, the txen pin should be held low (logic 0) to prevent forward signal transmission. after power has been applied to the amplifier, the gain can be set to the desired level by following the procedure provided in the spi programming and gain adjustment section. the txen pin can then be brought from logic 0 to logic 1, enabling forward signal transmission at the desired gain level. ramp pin and byp pin features the ramp pin (pin 15) is used to control the length of the burst on and off transients. by default, leaving the ramp pin unconnected will result in a transient that is fully compliant with docsis 2.0 section 6.2.21.2, spurious emissions during burst on/off transients . docsis requires that all between burst transients must be dissi- pated no faster than 2 s. adding capacitance to the ramp pin will add more time to the transient. the byp pin is used to decouple the output stage at midsupply. typically, for normal docsis operation, the byp pin should be decoupled to ground with a 0.1 f capacitor. however, in applications that may require transient on/off times faster than 2 s, smaller capacitors may be used, but it should be noted that the byp pin should always be decoupled to ground. transmit enable (txen) and sleep e le e sleep a al sleep sleep t sleep dapdss tdss ps apa t adz tpad t hz hzh hz dss hzedss a apdss t ap ass ss
rev. 0 ad8328 e9e states, ? spurious emissions from a transmitted carrier may occur in an adjacent channel that could be occupied by a carrier of the same or different symbol rates. ? tpc 3 shows the measured acp for a 60 dbmv qpsk signal taken at the output of the ad8328 evaluation board. the transmit channel width and adja- cent channel width in tpc 3 correspond to the symbol rates of 160 ksym /s. table i shows the acp results for the ad8328 driving a qpsk, 60 dbmv signal for all conditions in docsis table 6-9, adjacent channel spurious emissions . noise and docsis at minimum gain, the ad8328 output noise spectral density is 1.2 nv/ hz hzdsst spurious emissions in 5 mhz to 42 mhz , specifies the output noise for various symbol rates. the calculated noise power in dbmv for 160 ksym/s is: 20 12 160 60 66 4 2
+= log . ? . nv hz khz dbmv comparing the computed noise power of ? 66.4 dbmv to the +8 dbmv signal yields ? 7 4.4 dbc, which meets the required level set forth in docsis table 6-10. as the ad8328 gain is increased above this minimum value, the output signal increases at a faster rate than the noise, resulting in a signal-to-noise ratio that improves with gain. in transmit disable mode, the output noise spectral density is 1.1 nv/ hz st adaeal e tad ad pa pad t ad ad a dss tad dast t zad r zk kz in in 4 16 16 = . . ? v in + ad8328 v in e r4 z in figure 6. differential circuit differential signal from single-ended source the default configuration of the evaluation board implements a differential signal drive from a single-ended signal source. this configuration uses a 1:1 balun transformer to approximate a differential signal. because of the nonideal nature of real trans- formers, the differential signal is not purely equal and opposite in am pli tude. although this circuit slightly sacrifices even order harmonic distortion due to asymmetry, it does provide a con- ve n ien t way to evaluate the ad8328 with a single-ended source. the ad8328 evaluation board is populated with a toko 617db-a0070 1:1 for this purpose (t1). table ii provides typical r4 values for common input configurations. other input impedances may be calculated using the equation in figure 7. refer to figure 10 for an evaluation board schematic. to utilize the transformer for converting a single-ended source into a differential signal, the input signal must be applied to v in+ . r zk kz in in 4 16 16 = . . ? v in ad8328 r4 z in figure 7. single to differential circuit single-ended source although the ad8328 was designed to have optimal docsis performance when used with a differential input signal, the ad8328 may also be used as a single-ended receiver, or an if digitally controlled amplifier. however, as with the single-ended to differential configuration noted above, even order harmonic distortion will be slightly degraded. when operating the ad8328 in a single-ended input mode, v in+ and v in ? should be terminated as illustrated in figure 8. on the ad8328 evaluation boards, this termination method requires the removal of r2 and r3 to be shorted with r4 open, as well as the addition of 82.5 at r1 and 39.2 at r17 for 75 termination. table ii shows the correct values for r11 and r12 for some common input configurations. other input impedance configurations may be accommodated using the equations in figure 8. r z z r zr rz in in in in 1 800 800 17 1 1 = = + ? ad8328 r1 r17 v in + z in figure 8. single-ended circuit
rev. 0 e10e ad8328 table ii. common matching resistors differential input termination z in ( ) r2/r3 r4 ( )r 1/r17 50 open 51.1 open/open 75 open 78.7 open/open 100 open 107.0 open/open 150 open 165.0 open/open single-ended input termination z in ( ) r2/r3 r4 ( )r 1/r17 50 0 /0 open 53.6 /25.5 75 0 /0 open 82.5 /39.2 overshoot on pc printer ports the data lines on some pc parallel printer ports have excessive overshoot that may cause communications problems when pre- sented to the clk pin of the ad8328. the evaluation board was designed to accommodate a series resistor and shunt capacitor (r2 and c5 in figure 11) to filter the clk signal if required. installing visual basic control software install the cabdrive_28 software by running the setup.exe file on disk one of the ad8328 evaluation software. follow the on-screen directions and insert disk two when prompted. choose installation directory and then select the icon in the upper left to complete the installation. running ad8328 software to load the control software, go to start, programs, cabdrive_28 or select the ad8328.exe file from the installed directory. once loaded, select the proper parallel port to com- municate with the ad8328 (figure 9). figure 9. parallel port selection controlling gain/attenuation of the ad8328 the slide bar controls the gain/attenuation of the ad8328, which is displayed in db and in v/v. the gain scales 1 db per lsb. the gain code from the position of the slide bar is displayed in decimal, binary, and hexadecimal (figure 10). - figure 10. control software interface transmit enable and sleep mode the transmit enable and transmit disable buttons select the mode of operation of the ad8328 by asserting logic levels on the asynchronous txen pin. the transmit disable button applies logic 0 to the txen pin, disabling forward transmission. the transmit enable button applies logic 1 to the txen pin, enabling the ad8328 for forward transmission. checking the enable sleep l sleep ad sleep t t t
rev. 0 ad8328 e11e p1 2 p1 3 p1 5 p1 6 p1 7 p1 16 tp12 tp11 tp10 tp_v cc 1 a gnd1 v cc 1 tp_agnd1 p1 19 p1 33 p1 30 p1 29 p1 28 p1 27 p1 26 p1 25 p1 24 p1 23 p1 22 p1 21 p1 20 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ad8328 qsop txen v cc sleep byp nc v out + gnd ramp v out e gnd sdata clk v in + gnd gnd gnd v in e v cc daten gnd 6 4 cable_oa r15 0 r16 toko 617db-a0070 v cc 1 1 2 3 c13 0.1 f c8 10 f c10 0.1 f c9 0.1 f c11 c12 0.1 f tp9 c1a 0.1 f c2a 0.1 f r2 t1 r3 v in _a v in _a r1 r17 r4 78.7 r5 1k r6 0 r13 1k tp1 tp2 tp3 tp4 tp5 toko 458pt-1087 v cc r8 0 r10 0 r12 0 r14 0 c7 r11 1k r9 1k r7 1k c3 c4 c5 c6 figure 11. ad8328 evaluation board schematic
rev. 0 e12e ad8328 figure 12. primary side figure 13. component side silkscreen figure 14. internal power plane figure 15. internal ground plane figure 16. secondary side figure 17. secondary side silkscreen
rev. 0 ad8328 e13e 20-lead frame chip scale package [lfcsp] 4 mm 4 mm body (cp-20) dimensions shown in millimeters 1 20 5 6 11 16 15 bottom view 10 2.25 2.10 sq 1.95 0.75 0.55 0.35 0.30 0.23 0.18 0.50 bsc 12 max 0.25 ref 0.70 max 0.65 nom 0.05 0.02 0.00 1 .00 0.90 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.0 bsc sq controlling dimensions are in millimeters coplanarity 0.08 compliant to jedec standards mo-220-vggd-1 0.60 max 0.60 max 20-lead soic, 0.025 lead pitch [qsop] (rq-20) dimensions shown in millimeters and (inches) 24 13 12 1 8.74 (0.3341) 8.56 (0.3370) 6.20 (0.2441) 5.79 (0.2280) pin 1 3.99 (0.1571) 3.81 (0.1500) seating plane 0.25 (0.0098) 0.10 (0.0039) 0.30 (0.0118) 0.20 (0.0079) 0.64 (0.0252) bsc 1.50 (0.0591) max 1.75 (0.0689) 1.35 (0.0531) 0.20 (0.0079) 0.18 (0.0071) 1.27 (0.0500) 0.41 (0.0161) 8 0 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design outline dimensions
e14e
e15e
c03158e0e11/02(0) printed in u.s.a. e16e

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